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ISL5416
To Write to the Internal Registers:
1. Load the indirect write holding registers at direct address
ADD(2:0) = 0 and 1 with the data for the internal register
(32 bits).
2. Write the Indirect Write Address of the internal register
being addressed to direct address ADD(2:0) = 2 (Note: A
write strobe to transfer the contents of the Indirect Write
Holding Register into the Target Register specified by the
Indirect Address will be generated internally).
JTAG
JTAG: The IEEE 1149.1 Joint Test Action Group boundary
scan standard operational codes shown in Table 2 are
supported. A separate application note is available with
implementation details
JTAG Op Codes Supported
TABLE 6.
3. Wait 4 clock cycles before performing the next write to the
indirect write holding registers.
To Read Internal Registers:
1. Write the Indirect Read Address of the internal register
being read to direct address ADD(2:0) = 3.
2. Perform a read of the Indirect Read Holding Registers at
direct address ADD(2:0) = 0 and 1.
NOTE: After an indirect write to a single channel, the data
INSTRUCTION
EXTEST
IDCODE
SAMPLE/PRELOAD
INTEST
BYPASS
OP CODE
0000
0001
0010
0011
1111
can be read at direct addresses 0 and 1 after 4 clock
periods.
TABLE 7. STATUS BITS READ DIRECT ADDRESS 2 FOR (15:0)
15:8
7:6
5:4
3:2
1:0
REVISION CODE.
0x00h = prototype silicon.
0x01h = production silicon.
CHANNEL 3 STATUS. Bit 7 is always zero, bit 6 indicates data path saturation.
CHANNEL 2 STATUS. Bit 5 is always zero, bit 4 indicates data path saturation.
CHANNEL 1 STATUS. Bit 3 is always zero, bit 2 indicates data path saturation.
CHANNEL 0 STATUS. Bit 1 is always zero, bit 0 indicates data path saturation.
Bits 0, 2, 4, 6 are the OR-ing together of the individual data
path. Saturation bits listed in *01Fh (Table 14). These bits
are latched when set. Awrite to *01F clears the bit(s).
25
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